1. Field of the Invention
The present invention relates to a semiconductor memory device which rewritably stores data in a plurality or memory cells formed at intersections of a plurality of word lines and a plurality of bit lines, and particularly relates to a semiconductor memory device in which a memory cell array is configured so that an opposite electrode of a capacitor of each memory cell is directly connected to a bit line.
2. Description of the Related Art
Generally, a memory cell array of a DRAM includes a large number of memory cells formed at intersections of bit lines and word lines. Regarding the memory cell composed of one transistor and one capacitor, a structure in which an opposite electrode of the capacitor is directly connected to a bit line is proposed for the purpose of higher integration of the DRAM (e.g., see Patent References 1 to 3). On the premise of such a structure, when achieving a fine memory cell using a design rule such as 4F2 in order to manufacture a large capacity DRAM, it is desirable to employ a memory cell having a cylindrical capacitor structure. The memory cell having such a cylindrical capacitor structure is required to obtain a sufficient capacitance by forming the cylindrical portion with a sufficient height, for example, several μm. The cylindrical capacitor structure can be easily manufactured and occupies a smaller area in a plane so as to be appropriate for increasing the capacity of the DRAM.
Patent Reference 1: Japanese examined patent publication No. S58-32789
Patent Reference 2: Laid-open Japanese Patent Publication No. S60-98597
Patent Reference 3: Laid-open Japanese Patent Publication No. 2002-94027
However, since sides of cylinders of adjacent memory cells are arranged close to each other with a sufficient height when employing the conventional capacitor structure, the capacitance between the cylinders becomes relatively large. Then, the capacitance between the cylinders occupies a larger part of a coupling capacitance between bit lines, which causes an increase in coupling noise between bit lines when reading a signal through a bit line. Particularly, when many memory cells are connected to one bit line in a highly integrated memory cell array, the coupling capacitance between the bit lines accordingly increases, and influence of the coupling noise remarkably increases so that read operation is hindered. In this manner, when employing the cylindrical capacitor structure, it is a problem that operating margin decreases due to the coupling noise caused by the capacitance between the cylinders.